Models of computation (MOC) provide a framework to model various algorithms and activities, while accounting for and exploiting concurrency and synchronization aspects.. Further, a combination of these MOCs may be needed to truly represent a given Network-onChip (NOC) region and may further differ from a global to a local region. We have analyzed various models of computation (MOC) suitable for NoC. We have modeled a concurrent architecture for a customizable and scalable NOC in a system-level modeling environment using MLDesigner. MLDesigner provides a system level modeling platform, which allows one to integrate such MOCs together. We provide simulation results for various scheduling criteria, injection rates, buffer sizes, and network traffic. We abstracted area results for a 4×4 mesh based NoC from its Field Programmable Gate Arrays (FPGA) implementation. We have further quantified all the results and presented them from a system architect’s view.