International Journal of Engineering and Technology

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power dissipation. However, domino gates typically consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS logic circuits. In this work, a new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented for simultaneously reducing active & standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits in 65 nm deep submicron technology (DSM). The proposed technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Ground, power supply and threshold voltages are simultaneously optimized to minimize the power delay product (PDP). The proposed techniques are compared by performing detailed transistor simulations on benchmark circuits such as 1-bit Half Adder, 16-bit Adder, 16-bit Comparator, D-Latch, 4-bit LFSR using Microwind 3 and DSCH3 CMOS layout CAD tools.