International Journal of Engineering and Technology

Designing of modern digital circuits require high performance with reduced cost and minimal time to market. In order to achieve greater performance, timing analysis is done to meet all the timing constraints. It also leads to increase the complexity of emerging Very Large Scale Integration (VLSI) design. Timing analysis eliminates the occurrence of non-functional path. In this work, path tracing and clustering algorithms are proposed to optimize the critical path. The path elimination technique based on clustering is tested on some combinational benchmark circuits.