International Journal of Engineering and Technology

One of the increasingly difficult challenges in testing System-On-a-Chip (SoC) is dealing with the large amount of test vectors that must be stored in the tester and transferred between the testers. The test data bandwidth between the tester and the SOC is a bottleneck that can result in long test times when testing complex SOCs that contain many cores. Hence a test data compression and decompression scheme using reconfigurable multipliers has been presented in this paper. This scheme stores test vectors as a product of two deterministic vector seeds and uses the intermediate states of the multiplication of the vector seeds using the reconfigurable serial multiplier, to realize the test vector. Since multipliers are one of the widely used components in many SOCs, this method reduces significant hardware by exploiting the advantage of using the existing circuitry in the circuit under test for decompression. It provides a twofold advantage by reducing the amount of test data that needs to be stored on the tester and reducing the time for transferring test data from the tester to the circuit-under-test resulting in better encoding efficiency. Linear decompression with free variables is used. The encoding efficiency could be further explored with high percent of free variables. This scheme works best for circuits within built multipliers and significant reduction in hardware is observed. Experimental results obtained with ISCAS’89 benchmark shows the efficiency of this scheme on reduction of test data volume as well as the test time.