International Journal of Engineering and Technology

VLSI testing majorly concern with test time and power consumed during testing process. This paper presents efficient Decompressor architecture for low power test applications. The aim of the paper is to reduce the transition count of shift-in test pattern which reduces the power. X-factor circuitry, the concept adopt on the decompressor architecture in efficient way to improve performance of testing. The X-factor circuitry Decompressor design captured in VerilogHDL that targeted to TSMC 0.25 micron CMOS technology and results are analyzed.