e-ISSN : 0975-4024 p-ISSN : 2319-8613   
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ABSTRACT

ISSN: 0975-4024

Title : DESIGN OF 16-BIT LOW POWER ALU - DBGPU
Authors : Dhanabal R, Bharathi V, Saira Salim, Bincy Thomas, Hyma Soman, Dr Sarat Kumar Sahoo
Keywords : Adder/Subtractor, Column Bypassing, Compressor
Issue Date : Jun-Jul 2013
Abstract :
Arithmetic and Logic Unit (ALU) is one of the common and the most crucial components of an embedded system. Power consumption is a major design issue in the case of embedded systems. Usually ALU’s consists of a number of functional units for different arithmetic and logic operations which are realised using combinational circuits. Each of the functional unit performs a specific arithmetic or logic operation. In this paper the main concern is given for reducing the power of the adder and multiplier modules which are important functional units of ALU thereby reducing the overall power consumption without compromising the speed of the processor. The ALU circuit ensures the execution of either arithmetic or logic operation only at a time so that only one set of circuits is active at a time thus ensuring low power consumption. The entire ALU circuit is realised using Verilog HDL and power analysis is obtained through same.
Page(s) : 2172-2180
ISSN : 0975-4024
Source : Vol. 5, No.3