e-ISSN : 0975-4024 p-ISSN : 2319-8613   
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ABSTRACT

ISSN: 0975-4024

Title : Cadence Design of clock/calendar using 240*8 bit RAM using Verilog HDL
Authors : K.R.N.Karthik, M.Nagesh Babu, Fazalnoorbasha
Keywords : Automation technology, Digital Circuit, RAM.
Issue Date : Jun-Jul 2013
Abstract :
In the contrast of the modern day technology evolution the number of electronic components increasing on a system. New electronic control units (ECUs) are not only dedicated to entertainment, but also for increasing safety and comfort. More and more mechanical connections are replaced by electronic ones to save energy and increase comfort and security. All these electronic devices need a way of exchanging information on a fast, reliable and robust way. As there was a tremendous change in the technology day by day mainly in the field of chip designing and the automation technology as due to this the clock speeds are also rapidly increasing along with this power measures are also increasing so to manage this situation we are moving towards the clock/calendar. The clock/calendar circuit based on 2048-bit static RAM organized as 256 words by 8 bits .Address and data are transferred serially via the two-line bidirectional I2C-bus The built in word address register is incremented automatically after each written of read data byte .Addressing pin A0 is used for programming the hard ware address .allowing the connection of two device to bus without additional hardware This total module can be used as a real time clock of adjustable frequencies and can also replace the purpose of the counters on the digital based applications This is designed in verilog using Xilinx and cadence 90nm in LINUX environment
Page(s) : 2800-2806
ISSN : 0975-4024
Source : Vol. 5, No.3