International Journal of Engineering and Technology

This paper discuss a low power fault tolerant S-Box design for XTS- AES Algorithm, also called as P1619 Crypto Core was developed by SISWG (Security In storage Work Group) a Hard Disk Encryption standard algorithm. The faults are injected by Fault Injection Circuits which are considered in terms of Hardware Failures for the S-Box Transformation in every round during the circular shift operation for the block size of 128 bits and the technique applied to correct the fault is component reusability which never uses extra overhead components or spare circuits. The design has been synthesized in Cadence 90nm Technology with clock frequency about 1700MHz and the cell area obtained is 256980µm2 and the power consumption is 20198.53µW