International Journal of Engineering and Technology

This paper presents an architecture for K-best List Sphere Decoder (LSD) algorithm for Multiple Input Multiple Output (MIMO) Systems using Xilinx System Generator. We made use of an efficient bit-serial architecture, Distributed Arithmetic(DA) to reduce the computational complexity involved in the algorithm. The real-valued expanded channel matrix and received vectors are analyzed, designed and implemented using Xilinx Spartan-6 FPGA running at 100MHz. We compare the resource utilization of the conventional implementation of the algorithm with the proposed architecture for different number of layers. The conversion of multipliers into shift and adder units leads to area optimization and reduced power consumption. The total estimated power for our design is found to be 187mW.