International Journal of Engineering and Technology

Digital modulation is the first step in the digital communication system (DCS). The choice of modulation scheme among BPSK, QPSK, 8-QAM and 16-QAM are made based on the performance criterion such as bit-error-rate (BER) and bandwidth (BW) utilization. Hence the operating range of the DCS is improved by incorporating all the four modulation schemes in architecture. In this paper, a reconfigurable digital modulator is proposed for OFDM based DCS with more hardware efficiency (data rate per number of gates used in the architecture) by concurrent operation of different modulation schemes. Complex reconfiguration control logic is developed to maintain less idle period between the modes which is observed as maximum of 4 clock periods. The proposed reconfigurable modulator is implemented on Cyclone-II family of EP2C20F484C7 FPGA chip, which utilizes 34 logic elements (less than 1% ), consumes 78.73 mW of power at 200MHz clock frequency.