e-ISSN : 0975-4024 p-ISSN : 2319-8613   
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ABSTRACT

ISSN: 0975-4024

Title : A Complexity Reduction Method for Extended Min-Sum based Nonbinary LDPC Decoder
Authors : M Anbuselvi, S Salivahanan
Keywords : Linear block code, Iterative decoding, Non-binary LDPC decoder, Configuration Set, Min-Sum decoding algorithm
Issue Date : Dec 2013-Jan 2014
Abstract :
Nonbinary LDPC codes are a class of linear block codes having the performance closer to Shannon’s limit. Codes defined over higher order of Galois field, have increased computation complexity and thereby it put forth the challenges in efficient hardware realization of the decoder. In this paper, modifications in the Non-binary LDPC decoder to obtain reduced configuration sets, aimed to reduce the decoding complexity is proposed. Configuration sets are the possible combinations of the message sets that are involved in the parity check equation of LDPC decoder. Min-sum algorithm based decoder is modelled with the specification of IEEE 802.11n standard, with the codelength of 648, rate ½ for GF (4) Galois field, over the AWGN channel. The mathematical formulation of the proposed complexity reduction methodology is presented. The decoding performance of reduced configuration sets is analyzed and it is found that the complexity is reduced by an average of 83%, with negligible degradation in performance in terms of bit error rate.
Page(s) : 4605-4612
ISSN : 0975-4024
Source : Vol. 5, No.6