International Journal of Engineering and Technology

In this paper, a comparative study of two architectures proposed for multichannel reconfigurable FIR filter are performed in terms of complexity and speed. The proposed architectures, viz, dual port memory based LUT multiplier and accumulator based radix-4 multiplier architectures, are designed to reduce the complexity and to improve the speed of operation of multiplier used in multichannel reconfigurable FIR filter. Both the architectures accepts residues of given binary input in which the 3n-bit binary input is converted into three residues using binary to Residue Number System (RNS) converter, and then processed in three FIR sub filters constructed in direct form. The reconfigurable structure is achieved by combining Power of Two (PoT) FIR sub modules and altering the filter taps based on select signals. The proposed designs can be realized up to 20-taps and has been tested for 4, 8, 16 and 20 taps. The architectures have been realized in Verilog HDL and synthesized using Altera FPGA device Stratix II EP2S15F672C5. The performance comparison of two architectures shows that dual port memory based LUT multiplier architecture significantly reduces the area by 20% and accumulator based Radix-4 multiplier increases the speed by 90% regardless of the number of taps.