International Journal of Engineering and Technology

This paper addresses on two different architectures of digital decimation filter design of a multi-standard RF transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area and power. The proposed decimation filter architectures reflect the considerable reduction in area & power consumption without degradation of performance. The filter coefficients are derived from MATLAB , the filter architectures are implemented and tested using Xilinx SPARTAN FPGA . The Xilinx ISE 9.2i tool is used for logic synthesis and the Xpower analysis tool is used for estimating the power consumption. First, the types of decimation filter architectures are tested and implemented using conventional binary number system. Then the different encoding schemes i.e. Canonic Signed Digit (CSD) representation is used for filter coefficients and then the architecture performance is tested .The results of CSD based architecture show a considerable reduction in the area & power against the conventional number system based filter design implementation.