International Journal of Engineering and Technology

Two high speed architectures for Distributed Arithmetic (DA) based Finite impulse response filter (FIR) using a new shift accumulator are presented in this paper. The proposed shift accumulator (SA) composed of pipelined bit serial adder results in very high speed compared with existing left shift and right shift accumulators. First design is a DA look up table (LUT) based FIR filter with and without partitioning using the proposed shift accumulator. Second is a systolic array architecture for DA based FIR filter with proposed SA. Both the architectures were implemented using Xilinx Virtex 6vlx240tff1156-1 device. Number of slices, minimum period and maximum frequency were the performance metrics obtained for different filter orders for both the architectures and the results reveal that both the designs have yielded significant improvement in speed.