International Journal of Engineering and Technology

The FIR filter is a fundamental processing element in many Digital Signal Processing (DSP) systems. FIR filters are used in DSP applications ranging from image and video processing to wireless communication. Arithmetic circuits like adders and multipliers are basic building blocks of FIR filter. Digital systems are prone to errors and these are inevitable. The scheme of Error Tolerance (ET) states that some digital systems accept certain amount of errors and they are more efficient. The scheme of ET can be incorporated in DSP systems which accept that ET circuits can be used for applications in image, speech and video processing. As more devices becomes embedded or battery dependent, power consumption plays a vital role. Multipliers are the core of FIR filters; they consume a lot of energy and are generally complex circuits. This paper presents the implementation of 4-tap FIR filter using combination of conventional adder and Modified Error Tolerant Adder (META) with two different multiplier structures namely parallel array and Modified Wallace Tree Multiplier (MWTM). The highest sampling frequency achieved for the FIR filter is 505.05MHz by using combination of MWTM and META with lowest power consumption of 0.312mW. The design is implemented using Cadence® Virtuoso gpdk045nm CMOS technology. The implemented FIR filter is useful in various domains of DSP system such as audio, video, speech and image processing.