International Journal of Engineering and Technology

Due to millions of integration of components and shrinking process technology, nowadays leakage power tends to play a major role in total power consumption. In this paper various existing leakage power reduction techniques such as full sleep, sleepy stack, dual sleep, sleepy keeper and dual stack are analysed and two new techniques are proposed to reduce the leakage power in digital circuits by generating transistor grating technology. The digital circuits such as half adder and Full adder are designed using the proposed techniques in 32nm, 22nm and 16nm CMOS technologies and their performances are analysed.