International Journal of Engineering and Technology

Discrete Tchebichef Transform (DTT) is an orthogonal transform and is used in many applications like image and video compression, feature extraction, artefact analysis, blind integrity verification and pattern recognition. In comparison with DCT, DTT has better image reconstruction quality for certain class of images. Direct implementation of DTT requires large number of multiplications, which are time-consuming and expensive in a simple processor. To perform in real time, these large number of operations can be completely avoided in our proposed architecture. The proposed architecture uses distributed (DA) based technique which offers high speed and small area. The basic architecture consists of one dimensional (1D) row DTT followed by a transpose register array and another 1D column DTT. The 1D DTT structure only requires 15 adders to build a compressed adder matrix and is also ROM free. Compared with DCT architecture, the proposed architecture shows an improvement in speed and reduction in area by 5% on a Xilinx vertex-4 FPGA platform.