| Abstract |
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In this paper, a new technique for domino circuit is proposed, which has high noise immunity and consume low power without degrading the performance for wide fan-in dynamic gates. The proposed circuit utilizes the double stage domino technique, in which the domino circuit is divided into two stages: standard footed domino includes pull-down network and another standard footed domino includes one pull-down transistor and one keeper transistor. In between stage one and stage two, a simple current mirror is utilized. The wide fan-in gates are designed in 90-nm gpdk technology and simulation result of 64-bit OR gate shows 78% power reduction and Unity Noise Gain (UNG) increased by 3.25 times, compares to the standard domino circuits, while simulation carried out under same delay and process corner. And the proposed technique maintains Figure of Merit (FOM) of 13.13 |
