International Journal of Engineering and Technology

Layout design of an Integrated Circuit (IC) is the representation of IC in terms of geometric shapes which corresponds to the pattern of metal, polysilicon, oxide and semiconductor layers that constitutes the components of IC. Layout optimization plays a key role in producing an IC with less inter connect delay, parasitic effect, signal integrity issues and power dissipation etc. This research work proposes the methodology through which unwanted white space present in the layout has been minimized which tends to reduces the total area of the layout. The proposed methodology has been checked by designing the single ended differential amplifier as an example circuitry and by using Cadence® virtuoso® 64 tool. The proposed methodology reduces the layout area by applying three methods together and the methods applied are i) working towards minimum distance rule ii) introducing jogs and iii) depletion sharing. After using above mentioned methodologies together in Single ended differential amplifier, the total area of the layout has been reduced to 77.81% when compared to original schematic driven layout of the same.