International Journal of Engineering and Technology

In this paper, a hardware oriented realization, for the real time two dimensional (2-D) state space general model systems, is proposed. The proposed design of 2-D systolic array utilizes processing elements (PEs) which is simpler in use. The number of PEs is made equal to the multiplication of both the number of rows and column of the considered architecture. The proposed architecture provides excellent performance in terms of speed, efficiency and accuracy. Further, different designs of PEs are also proposed for state space feedback controller and unified structure. The unified structure can be work as state space systems as well as feedback controller after applying some control signals. It is shown that the area of unified structure is slightly more than that of structure-I and II taken separately. The ASIC synthesis results shows the proposed unified structure for system/controller of order 7 has taken approx 22% more area and 50% less area than state space system and controller with feedback respectively. Finally, the proposed architecture is implemented and analyzed using Verilog-HDL and Synopsis Design Compiler with 90nm TSMC target libraries.