ABSTRACT

Multiplier is one of the important circuits used in digital electronics field particularly in digital signal processing such as convolution, filtering and analysis of frequency. There are different kinds of algorithms used in multipliers to attain better performance such as Array, Booth, Sequential, Dadda and Wallace tree multiplier were the different types of multipliers created using CMOS logic. The Dadda multiplier is a most recent and advanced multiplier circuit which can be used to reduce partial product bit further it will reducetotalnumber of iteration within certain limitations. The enhanced Dadda multiplier with 5:2 compressors further reduces partial product bit and no. of state transitions and the proposed method will minimize the usage of total number of logic gates used. ThoughArray, Wallace tree multiplier offers higher power consumption. Additionally, Daddamultipliers with 5:2 compressors minimize delay, power consumption and provide high robustness. The simulation was done by using Xilinx tool.