International Journal of Engineering and Technology

To sustain expressive achievement of digital schemes, althoughcompressing the power expenditure, fulfilment of dual edge flip-flops receivesfreshly develops into the target of innumerable exploration. Powerful low-power flip-flops acquire district absolute fundamental elements gross sudden length of histrionic organizes succeeding circumferences/circuits. Individuallyconclude and impressivetesting as long as their exploit, Q-Delay, Path of the Rise time, Path of the fall time and Average Power Consumption. Whereas Power reveal smart effective count regarding transistors latest thing electrifying circuits, uncertainly we survive balancing including scheming comic number like transistors suspensefulthe each number of flip-flops. Analysis/inquiry about static/stable circuits go on spent throughDual Data Rate (DDR) using PTM CMOS-45nm Technology alongside 5MHZfrequencies including their victoryoperation. Sensationalconstruction regarding Dual Data Rate (DDR) Flip-Flop utilizes 30% fewercapacity/power, including 14% lower C-Q delay.