International Journal of Engineering and Technology

In this paper, a 40 bit tag comparator is proposed. The proposed tag comparator has minimum leakage current. It also provides greater noise immunity without any reduction in the speed when compared to high speed domino logic, leakage current replica, keeper domino logic, diode footed domino logic and current comparison based dual-rail domino logic. The proposed circuit works by taking in to account the relation of mirrored current of the pull down network (PDN) with the leakage current flowing in the worst case. Simulation of the proposed 40 bit tag comparator is done using gpdk_90 nm CMOS process technology. The simulation results of proposed circuit shows 70% reduction in power consumption, 8% reduction in required area and 22% lowering down of propagation delay compared with the conventional standard footless domino having equal robustness condition. PMOS keeper transistor of conventional structures is eliminated as a result of which the figure of merit of the proposed circuit shows an improvement of 6.45 in contrast with the conventional domino circuit. The proposed circuit consumes less power with improved speed and is suitable for fully-associative caches consisting of huge number of tag comparators.