International Journal of Engineering and Technology

This paper propounds the role of test vectors with minimal power for Built-In-Self-Test (BIST) applications. This method signifies Test-Per-Clock (TPC) based test vectors using Multiple Single Input Change (MSIC). MSIC patterns are generated by using EX-OR operation of counter and test pattern algorithms like Linear Feedback Shift Register (LFSR), Bit-Swapping LFSR (BSLFSR), Hybrid Cellular Automata (HCA). These patterns are used to reduce number of transitions in the test patterns that are generated. The preferred method uses Test-Per Clock scheme for generating MSIC patterns. TPC reduces the power consumption during test mode. The seed generator used in TPC is modified LFSR’s i.e., BS-LFSR and Cellular Automata (CA). Using CA we also present a variation on a Built-In-Self-Test (BIST) technique, which is based on a pseudo random number generator inferred from a one-dimensional cellular automata array. We proposed Hybrid Cellular Automata (HCA) using the rules 90 and 150 to generate the pseudo random patterns. In addition, it is noted that CA implementations exhibit data compression properties similar to the LFSRs and that they display locally and with topological regularity significant attributes for a VLSI implementation. In this proposed method, LFSR is replaced with BS-LFSR and CA. BS-LFSR is composed of an LFSR with a multiplexer. This reduces the number of transitions by 33.3% using MSIC whereas CA has more randomness compared with the LFSR. BSLFSR and CA are used in TPC.