International Journal of Engineering and Technology

This Paper presents the design and simulation of low power successive approximation register for the Analog to Digital Converters (ADC) using 0.18um CMOS Technology. This acts as digital part of successive approximation ADC. The principle of the Successive Approximation Register (SAR) circuit is to determine the value of each bit of the ADC in a sequential manner, depending on the value of the comparator output. If an N bit analog to digital converter is implemented, there are 2N possible conversion output values, which means that the SAR needs at least 2N states and so, as minimum, N FFs. For N bit SAR ADC, the sequence/code register SAR structure requires 2N Flip-Flops and hence power consumption and area occupied is more and Non redundant SAR structure requires N Flip-Flops and a little combinational Logic and hence power consumption is less and area occupied is also less compared to that of Conventional. For 10 bit SAR architecture, the dynamic power consumed by sequence/code register SAR structure is 63.4359uW and non reduandant SAR architecture is 49.2569 uW. The total power reduction using non redundant architecture is 22.35%.